During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well known patterning and etching processes. In these processes, a photoresist (PR) material is deposited on the wafer and is then exposed to light filtered by a reticle. The reticle is generally a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials, the exposed regions are removed, and in the case of negative photoresist materials, the unexposed regions are removed. Thereafter, the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material, and thereby define the desired features in the wafer.
The minimum feature size of integrated circuits (ICs) continues to shrink with each generation of semiconductor wafer processing improvements. As transistors and metal lines get smaller and move closer together, previously insignificant third-order variables now dominate IC design and fabrication. One problem that has arisen is “line end shortening” (LES). FIGS. 1A and 1B illustrate one line end shortening problem. LES is characterized as the difference between the actual printed position of the end of a line and the intended (designed) position. FIG. 1A illustrates the design of a transistor 10 with a polysilicon line 12 running from left to right, that may form a gate region used to electrically couple an upper diffusion region with a lower diffusion region.
FIG. 1B illustrates the actual printed image that results from the design with the dotted lines 16 illustrating the desired design. Due to the etch effects and photoresist pullback, there is a significant amount of line end shortening 14. An LES ratio may be defined, with reference to FIG. 1B, as (Y-Y1)/(X-X1), which is the ratio of the reduction of the length to the reduction of the width, which is currently greater than 2.
FIGS. 2A and 2B illustrate another LES problem. The design illustrated in FIG. 2A may have a photoresist line 20 having a width W1, side walls 24, and line ends 22 between an active source 26 and drain 28. The resulting printed image is illustrated in FIG. 2B. The resulting image has a photoresist line 30 with a width W2, sidewalls 32, and line ends 34. The width, W3, between the design line end 22 and the printed image line end 34 results in a gap between the source 26 and drain 28 that causes leakage and failure of the device. As stated above, and illustrated in FIG. 2B, LES at W3, is much greater than the difference between W1 and W2. Thus, LES is greater at the line ends 22 as compared to the sidewalls 24. Although extensions may be added to the line to print a longer photoresist line, it is typically not possible because there is not enough room in the mask design to compensate for LES. The LES ratio may be defined as (W1-W2)/(2·W3).
Others have added “hammer heads” onto line ends to compensate for LES. However, hammer heads may give rise to the design rule violations that can potentially cause bridging between the hammer head and polysilicon line. Although this bridging problem may be alleviated by a separation between the hammer head and polysilicon lines, the separation would increase the size of the circuit element, which means fewer circuit elements that can be integrated into a semiconductor device. Additionally, the use of hammer heads may cause larger line width roughness.
LES may result in degraded device performance, reduced reliability, lost yield, leakage in the device, limitations on critical dimensions (CD) and other related problems.